With improvements in integration of a semiconductor device and the further development of manufacturing and design techniques, there has been an attempt to construct a system using one chip. A technique relating to a one-chip system has been developed focusing on integrating a controller and circuits which operate with a low voltage in one chip.
However, for the reduction in the weight and size of the system, it may become necessary to form a circuit unit for controlling the power supply of the system, that is, input and output ports and a main circuit as one chip. Since the input port and the output port are circuits to which a high voltage is applied, the input port and the output port may not be formed of general low-voltage complementary metal-oxide-semiconductor (CMOS) circuits and high-voltage power transistors.
Accordingly, in order to reduce the size or weight of the system, the input and output ports of the power supply and the controller may be formed as one chip. To this end, a power IC technique may be provided in which a high-voltage transistor and a low-voltage CMOS transistor circuit are formed as one chip.
The power IC technique improves the structure of a vertical double-diffused metal-oxide-semiconductor (VDMOS, or Vertical DMOS) device which is a discrete Power transistor of the related art. A lateral DMOS (LDMOS) may be implemented in which a drain is arranged laterally to allow a current to flow laterally, and a drift region is provided between the channel and the drain, thereby securing high-voltage breakdown.
The LDMOS device of the related art will be described with reference to the accompanying drawings.
FIG. 1 is a sectional view illustrating the structure of an LDMOS device of the related art.
Referring to FIG. 1, an epitaxial layer (P-EPI) 70 may be formed in a semiconductor substrate (P-SUB) 100 in which an active region is defined by a device isolation film 60, and an NBL (N-Buried Layer) 90 and an HV PWELL (High Voltage P-WELL) 80 may be formed on and/or over the epitaxial layer 70.
A gate pattern 40 may be formed on and/or over the semiconductor substrate 100 to overlap the device isolation film 60. A P-body 30 may be formed in the HV PWELL (High Voltage P-WELL) 80 on one side of the gate pattern 40, and a source 5 may be formed in the P-body 30. An MV NWELL (Medium Voltage N-WELL) 50 may be formed in the HV PWELL (High Voltage P-WELL) 80 on the other side of the gate pattern 40, and a drain 10 may be formed in the MV NWELL 70.
The LDMOS device of the related art has a structure in which a deep sink region (DEEPN+) 20 separated from the drain 10 by the device isolation film 60 is used as a guard ring, thereby preventing parasitic PNP operation. In other words, if the deep sink region 20 is used as a guard ring, when a current flows backward in an inductor, that is, when an electron current is generated, holes are recombined in the NBL 90, and unrecombined electrons flow into the deep sink region 20 to prevent the electron current from flowing into the substrate, thereby preventing parasitic PNP operation.
FIG. 2 is a graph illustrating the correspondence relation (BVceo) between a collector current Ic and a voltage Vc across a collector and an emitter in the LDMOS device of the related art. FIG. 3 is a graph illustrating the correspondence relation (Ic-Vce) between a collector current Ic and an output voltage Vc in the LDMOS device of the related art.
Referring to FIGS. 2 and 3, it can be understood that the collector carries out current sweep in the NBL, BVceo is equal to or higher than 25 V, and the Ic-Vc curve stably operates at a voltage equal to or higher than 15 V. Meanwhile, as shown in FIG. 1, when a P-epi terminal is provided, the parasitic NPN undergoes a situation in which the base operates on both sides.
FIG. 4 is a sectional view illustrating a case where an ISO is not a deep sink region in the LDMOS device of the related art. As illustrated in. FIG. 4, when an ISO is not a deep sink region (Deepn+), a PN junction is formed between a deep well (DNWELL) 420 and a semiconductor substrate 410, such that an electron current leaks to the semiconductor substrate 410. This is because a voltage drop occurs in a current flowing in the deep well 420 due to high resistance in the deep well 420, and a voltage equal to or greater than 0.7 V is applied between the deep well 420 and the semiconductor substrate 410 such that the PN junction is formed.
That is, in a reference region 400, since resistance Rs of the deep well 420 is, for example, very high, at about 2450 ohm/sq, it may be necessary to perform diffusion or ion implantation using a POCl3 (phosphorus oxychloride) solution to form a deep sink region.
In the LDMOS device of the related art which operates in the above-described manner, as illustrated in FIG. 1, it may be necessary to perform the POCl3 process to form the deep sink region 420. The POCl3 process may cause an increase in a process time, resulting in an increase in process costs and consequently reducing cost efficiency.